Method for stabilizing high pressure oxidation of a semiconductor device

ABSTRACT

A method and apparatus for preventing N 2 O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N 2 O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N 2 O and a temperature range of 600° to 750° C., which are the conditions that lead to the N 2 O going super critical. By preventing the N 2 O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of application Ser. No.10/212,892, filed Aug. 5, 2002, pending, which is a continuation ofapplication Ser. No. 09/798,445, filed Mar. 2, 2001, pending, which is adivisional of application Ser. No. 09/386,941, filed Aug. 31, 1999, nowU.S. Pat. No. 6,291,364, issued Sep. 18, 2001.

BACKGROUND OF THE INVENTION

[0002] The present invention relates generally to oxidizing asemiconductor surface during an anneal processing step and, moreparticularly, the present invention relates to stabilizing a highpressure oxidation step using nitrous oxide gas within a temperaturerange of 600° to 750° C.

[0003] Advanced semiconductor devices, such as high density dynamicrandom access memories (“DRAMs”), impose severe restrictions on thetimes, temperatures, and atmospheres of all thermal process steps. DRAMsare comprised of a plurality of memory cells. Each memory cell isfurther comprised of a field effect transistor and a capacitor. It iswell known in the art of semiconductor fabrication to use planarcapacitors within DRAM cells; however, in DRAM cells that utilizeconventional planar capacitors, more integrated circuit surface area isdedicated to the planar capacitor than to the field effect transistor.

[0004] As the density of components in integrated circuit memoriesincreased, the shrinkage of memory cell size resulted in a number ofother problems in addition to the problems associated with a smallercapacitor. Among the resulting problems was that of dopant diffusing outof the semiconductor material when forming the transistors of the memorycells. In order to form transistors, dopants must be implanted inregions of the semiconductor materials. The dopant, however, tends todiffuse out of the transistor regions when the transistors are heatedduring subsequent integrated circuit processing steps. For example,dopant diffuses from the semiconductor material during the reoxidationanneal of the dielectric layer of the cell capacitor.

[0005] Silicon nitride is used as a dielectric layer because it has lessdesirable leakage current properties than silicon dioxide. Further, athin oxide layer is grown upon the dielectric layer by reoxidizing alayer of silicon nitride enough to form this oxide layer to furtherreduce the leakage current of the silicon nitride film.

[0006] Once the proper amount of silicon oxide and nitride oxide havebeen grown upon the surface to form the dielectric layer, a reoxidationanneal step is necessary to reduce the imperfections typically occurringduring the initial reoxidation growth stages.

[0007] One method to provide the silicon dioxide film is to perform ahigh pressure chemical vapor deposition (HVCVD) process step on thesemiconductor device. The formation of the cell dielectric, as well astransistor gate oxides and reoxidation steps in other processingapplication steps, is subjected to high pressures in excess of oneatmosphere, typically between five (5) atmospheres to twenty-five (25)atmospheres, where an atmosphere is represented as a pressure of 760Torr. An atmosphere of pure N₂O is introduced under such pressures in atemperature range of 600° C. to 800° C. The desired reaction is:

N₂O→N₂+O⁻; 2N₂O→2NO+N₂

[0008] This allows the oxygen to react with the silicon surface, formingthe silicon dioxide layer.

[0009] Unfortunately, as the N₂O reaction proceeds, it can becomeuncontrollable under certain circumstances; specifically, the N₂Oreaction can become supercritical, which gives rise to high pressurespikes within the high pressure oxidation furnace. These high pressurespikes abort the high pressure furnace runs and prevent the furnacesfrom operating in pure N₂O in the temperature range of 600° C. to 750°C. As the concentration of unreacted N₂O builds up in the high pressureoxidation furnace, it reaches a critical point where the disassociationreaction is self-propitiating. This reaction goes from

2N₂O→2NO+N₂

[0010] Once the concentration of unreacted N₂O exceeds this criticalpoint, the uncontrolled reaction occurs and generates pressure spikesthat may explode a furnace tube of the high pressure oxidation furnace.An exploding furnace tube results in ruined product as well as dangerousworking environment conditions for personnel.

[0011] Accordingly, a method and apparatus is needed that reduces, ifnot, prevents the unreacted N₂O from becoming super critical to ensurethe uniform processing of the semiconductor wafers.

BRIEF SUMMARY OF THE INVENTION

[0012] According to the present invention, a method and apparatus forpreventing N₂O from becoming super critical during a high pressureoxidation stage within a high pressure oxidation furnace are disclosed.The method and apparatus utilize a catalyst to catalyticallydisassociate N₂O as it enters the high pressure oxidation furnace. Thiscatalyst is used in an environment of between five (5) atmospheres totwenty-five (25) atmospheres N₂O and a temperature range of 600 to 750°C., which are the conditions that lead to the N₂O going super critical.By preventing the N₂O from becoming super critical, the reaction iscontrolled that prevents both temperature and pressure spikes. Thecatalyst can be selected from the group of noble transition metals andtheir oxides. This group can comprise Palladium, Platinum, Iridium,Rhodium, Nickel, Silver, and Gold.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 depicts a block diagram of a high-pressure furnace with acatalytic matrix sleeve inserted therein;

[0014]FIG. 2 depicts a grid arrangement of the catalytic matrix sleeveused in FIG. 1; and

[0015]FIG. 3 depicts a high pressure furnace that uses a catalyticmatrix screen in an alternative embodiment.

DETAILED DESCRIPTION OF THE INVENTION

[0016] With reference to drawing FIG. 1, a high pressure furnace 10 forchemical vapor deposition is illustrated. The furnace 10 comprises areactor vessel or furnace tube 12 and a front and rear flange assembly14 and 16, respectively. Wafers are positioned within furnace tube 12.Front flange assembly 14 includes various gas inlets. The gas inletsterminate right at the flange assembly. Gas is injected into furnacetube 12 and immediately adjacent the inlet flange. An exhaust port 18connects to a suitable pump for exhausting gases from furnace tube 12.Placed within furnace tube 12 is a catalyst matrix liner 20 that iscomprised of a catalyst element that catalyzes N₂O gas dissociation asthe gas enters the furnace tube 12.

[0017] Furnace 10 operates under high pressure and temperatures. Thepressure is above one atmosphere and ranges from five (5) atmospheres totwenty-five (25) atmospheres. The temperature range is from 600° C. to750° C. These pressures and temperatures can be greater or less, with atransition through the stated temperature range. The importance of usingcatalyst matrix liner 20 is to protect against pressure and temperaturespiking occurring within the furnace tube 12 of the furnace 10 duringsuch pressure and temperature ranges of operation of the furnace 10.

[0018] Catalyst matrix liner 20, which is also shown in drawing FIG. 2,is comprised of a catalyzing agent that causes the N₂O gas in thefurnace 10 to react to form the base components of nitrogen and oxygenof the N₂O gas according to the following reaction:

N₂O→N₂+⁻+Catalyst

[0019] The use of the a catalyst constrains the chemical reaction fromrunning away or becoming uncontrollable, which would cause a pressureand temperature surge within the furnace 10. Such surges must be avoidedas they destroy the semiconductor materials under fabrication within thefurnace 10 as well as causing the possible destruction of the furnacetube 12.

[0020] Catalyst materials are selected from the group consisting ofPalladium, Platinum, Iridium, Rhodium, Nickel, and Silver. Gold also canbe used as a catalyst, but should be avoided as gold contaminates thesilicon used in the wafers on which semiconductor devices are formed.Additional catalysts include perovskites, CaTiO3, a natural or syntheticcrystalline mineral composed of calcium dioxide and titanium dioxide.When using a Tantalum compound to form the gate oxide or the celldielectric for the transistors of a semiconductor device, a tantalumoxide is produced in the N₂O atmosphere in the furnace 10. The oxygenfrom the N₂O combines with the tantalum oxide according to the followingreaction:

2TaO_(x)+O₂→Ta₂O₅+Catalyst

[0021] The use of the catalyst material helps to drive this reactionnearly to full stoichiometry. When used with the a Barium StrontiumTitanate compound, the catalyst allows the oxidation to produce:

Ba_(x)Sr_(1-x)TiO₃

[0022] which is driven to full a stoichiometry reaction as well.

[0023] The catalyst matrix liner 20 of drawing FIG. 2 is shown to be ina honeycomb or hexagonal geometry. This particular geometry is usedbecause of its ease of manufacture and its strength and stability. Othergeometric shapes are also possible, such as, for example, circles,ovals, rectangles, diamonds, and other various types of polygonalshapes. Referring to drawing FIG. 3, illustrated is an alternativeembodiment of catalyst matrix liner 20 with respect to its locationwithin furnace 10. In this embodiment, catalyst matrix liner 20 isplaced next to the gas inlets of front flange assembly 14. This positionallows for the nitrous oxide to strike the catalyst matrix liner 20 asthe gas enters the furnace chamber or tube 12 of furnace 10. Again, asstated previously, the contents of furnace 10 in drawing FIG. 3 areunder high pressure and temperatures as described herein.

[0024] The catalyst matrix liner 20 can be made having a honeycomb orhexagonal base or supporting material base from a material, such asstainless steel, which is subsequently plated with the desired catalyticmaterial as described herein. Other well known materials may be used forthe honeycomb or hexagonal catalyst matrix liner that are suitable forsuch use as a substitute for stainless steel include aluminum oxide, orother suitable structural ceramics where the catalyst is embeddedtherein.

[0025] The furnace 10 is useful during gate oxidation in growing eithera nitride layer or an oxide layer, or both. Further, cell dielectriclayers can also be oxidized under safe conditions using the furnace 10.Additionally, reoxidation can be performed safely under the desiredtemperature and pressure constraints as described herein within thefurnace 10. The advantages of using high pressures within the statedtemperature range is that the semiconductor material is not subjected tothe high heat loads of temperature in excess of 800° C., which can warpand damage the wafers as well as inhibit the oxide growth layer.Additionally, the reactions within the furnace 10 can be easilycontrolled during operation without undesired reactions occurring.Additionally, the high pressure oxidation process minimizes the time thewafers are subjected to high temperatures and helps to minimize anyundesirable diffusion of dopants whose rate of diffusion increases withincreases in temperature.

[0026] While the preferred embodiments of the present invention havebeen described above, the invention defined by the appended claims isnot to be limited by particular details set forth in the abovedescription, as many apparent variations thereof are possible withoutdeparting from the spirit or scope thereof.

What is claimed is:
 1. A method for oxidizing one of a gate dielectriclayer and a cell dielectric layer on a portion of a silicon substrate inan atmosphere comprising: raising the temperature of said siliconsubstrate to a temperature of at least about 600° C.; providing a gasatmosphere of N₂O, said gas atmosphere of N₂O having a pressure of atleast about five atmospheres for contacting at least a portion of saidsilicon substrate; and contacting a portion of said gas atmosphere ofN₂O with a catalytic matrix consisting of one or more metals.
 2. Themethod according to claim 1, further comprising: forming an oxide layeron said one of a gate dielectric layer and a cell dielectric layer on aportion of said silicon substrate.
 3. The method according to claim 1,further comprising: forming an oxide layer on a portion of said siliconsubstrate.
 4. The method according to claim 1, further comprising:oxidizing a tantalum oxide layer on a portion of said silicon substrate.5. The method according to claim 1, further comprising: forming a bariumstrontium titanium oxide layer on a portion of said silicon substrate.6. The method according to claim 1, further comprising: forming astrontium bismuth titanate oxide layer on a portion of said siliconsubstrate.
 7. The method according to claim 1, wherein said catalyticmatrix is selected from the group consisting of lead, platinum, iridiumand palladium.
 8. The method according to claim 1, wherein saidcatalytic matrix is selected from the group consisting of rhodium,nickel, and silver.
 9. A method for oxidizing a portion of a siliconsubstrate comprising: changing the temperature of said silicon substrateto a temperature in a range of about 600° C. to 800° C.; providing a gasatmosphere of N₂O, said gas atmosphere of N₂O having a pressure of atleast about five atmospheres; and contacting a portion of said gasatmosphere of N₂O with a catalytic matrix consisting of at least onemetal.
 10. The method according to claim 9, further comprising: forminga nitride layer on a portion of said silicon substrate.
 11. The methodaccording to claim 9, further comprising: forming an oxide layer on aportion of said silicon substrate.
 12. The method according to claim 9,further comprising: forming a tantalum oxide layer on a portion of saidsilicon substrate.
 13. The method according to claim 9, furthercomprising: forming a barium strontium titanium oxide layer on a portionof said silicon substrate.
 14. The method according to claim 9, furthercomprising: forming a strontium bismuth titanate oxide layer on aportion of said silicon substrate.
 15. The method according to claim 9,wherein said catalytic matrix is selected from the group consisting oflead, platinum, iridium and palladium.
 16. The method according to claim9, wherein said catalytic matrix is selected from the group consistingof rhodium, nickel, and silver.
 17. A method for oxidizing a portion ofa silicon substrate comprising: providing an atmosphere having atemperature of at least about 600° C.; providing a gas atmosphere ofN₂O, said gas atmosphere of N₂O having a pressure of at least about fiveatmospheres; contacting at least a portion of said silicon substratewith a portion of said gas atmosphere of N₂O having a pressure of atleast about five atmospheres; and contacting a portion of said gasatmosphere of N₂O with a catalytic matrix consisting of at least onemetal.
 18. The method according to claim 17, further comprising: formingat least one of a nitride layer on a portion of said silicon substrate,oxide layer on a portion of said silicon substrate, a tantalum oxidelayer on a portion of said silicon substrate, a barium strontiumtitanium oxide layer on a portion of said silicon substrate, and astrontium bismuth titanate oxide layer on a portion of said siliconsubstrate.
 19. The method according to claim 17, wherein said catalyticmatrix is selected from the group consisting of lead, platinum, iridiumand palladium.
 20. The method according to claim 17, wherein saidcatalytic matrix is selected from the group consisting of rhodium,nickel, and silver.